Ordered successive interference cancellation （OSIC） is a commonly utilized signal detection algorithm in multiple input multiple output （MIMO） systems. However， the algorithm’s performance in terms of throughput and latency is constrained by the computational complexity of the channel matrix inverse operation. Therefore， matrix inverse decomposition pre-processing with low computational complexity and high speed is the key to hardware implementation of the algorithm. In this paper， we adopt a hardware-accelerated matrix pre-processing scheme for sorted orthogonal triangle （QR） decomposition of the channel matrix， in which the sorting process introducing a fast estimation method for complex-valued 1-norm to eliminate complex modulus computation. The QR decomposition process uses a deeply pipelined coordinate rotation digital computer （CORDIC） iterative method to eliminate the element vectorization and nulling rotation angle computation in the Givens rotation process， thus a pipeline circuit structure with a reusable Givens rotation structure for QR decomposition is designed， obviating the necessity for multipliers in the matrix decomposition process. Simulation results demonstrate that the OSIC enhancement algorithm proposed achieves the bit error rate（BER） performance comparable to that of the signal-to-noise ratio-based OSIC detection algorithm. The CORDIC iterative Givens rotation structure proposed in this paper can achieve highly time-sharing multiplex. It significantly improves the system parallelism and reduces the resource consumption， and the system design clock attains up to 250 MHz， and the matrix decomposition throughput reaches 1.88 M Matrices/s， meeting the processing throughput and latency requirements of 4 or more antennas MIMO systems at the receiver.