Storage Rate Optimization Design Based on FPGA+SD3.0 Protocol
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School of Aerial Survey, Chinese Academy of Surveying and Mapping, Beijing 100036,China

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TN492

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    Abstract:

    The storage solutions in the market cannot meet the requirements for storage speed and device volume with specific functional requirements. So, we design a SD3.0 version TF card controller based on field programmable gate array(FPGA)control, aiming to achieve higher-speed data storage while occupying the smallest volume. Through a self-designed small data acquisition card, the 24-bit-wide data are finally stored into the TF card through DDR3, FIFO, RAM, and two-level buffer. This paper introduces the scheme design from two aspects of hardware and software. The former mainly includes the circuit technology, acquisition card index and board-level signal integrity verification; the latter mainly includes the storage process, RTL-level verification and the TF card test. Experimental results show that the proposed PCB circuit can provide the voltage conversion and data storage functions required by SD3.0 protocol, and the board has stable functions and high integration. The speed of TF cards exceeds 60 MB/s with a long time. It has stable performance and good versatility. The experiment meets the design requirements, and it can also provide a solution for miniaturized storage experiments.

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XU Lu, LIU Zhengjun, CHEN Yiming. Storage Rate Optimization Design Based on FPGA+SD3.0 Protocol[J].,2022,37(4):926-934.

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History
  • Received:March 23,2021
  • Revised:July 13,2022
  • Adopted:
  • Online: July 25,2022
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