An IP core of low hardware-cost 256-point fast Fourier transform （FFT） processor is designed based on field programmable gate array （FPGA）. In order to reduce the complexity of twiddle factor calculation， the radix-2⁴ algorithm based on decimation in frequency and the single-path delay feedback （SDF） pipelined architecture are adopted. For reducing hardware-cost， a cascade canonical signed digit （CSD） complex multiplier instead of conventional Booth multiplier is proposed for the operation of twiddle factor W256i multiplied by the corresponding sequences. Also， the proposed cascade CSD multiplier can remove read only memory （ROM） for storing coefficients of twiddle factors. The IP core is synthesized by using QUARTUS PRIME tool and is implemented on Cyclone 10LP FPGA. The result shows that the proposed FFT design can work under a maximum clock frequency of 100 MHz which occupies only 3 978 logic elements （LEs） and 6 456 memory bits （MBs） hardware-resource for 24-bit signed number FFT operation.