Aiming at the problems of expensive hardware costs and poor real-time performance for the channel fading twin technology in real communication scenarios， based on the greedy coordinate rotation digital computer （CORDIC） algorithm and sum of frequency modulated model， a discrete non-stationary complex fading channel emulation scheme is developed. Furthermore， large scale complex exponential computations are realized in the field programmable gate array （FPGA） hardware platform. By introducing the domain folding technique， the greedy angle recording unit and a full parallel pipeline structure， the hardware resource consumption and real-time performance are significantly improved. In addition， the hardware resource can be further optimized by adopting the compact architecture with time-division and multi-rate scheme. Compared with the traditional look up table （LUT） method， hardware resource consumption is greatly reduced from 17.89% to 6.71%. Meanwhile， the hardware latency is reduced by 65.625% than classic CORDIC algorithm. The hardware measurement results show that the statistical properties of channel output， i.e.， the probability density function provides a good agreement to the theoretical ones.