FPGA Based Single Event Upset Simulation Technology
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College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 211106, China

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TN47

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    Abstract:

    Due to the increasing complexity of aerospace exploration, integrated circuits are applied in many aerospace electronic systems such as deep space communication and attitude control. With the further shrinking of integrated circuit technology, the probability of errors in circuit due to single event effects has become higher. Evaluating the sensitivity of integrated circuits to single event upset (SEU) is of great significance to the development of aerospace. The continuous increase of circuit scale and the improvement of system function integration pose severe challenges to the speed of evaluation. For this reason, this paper proposes a fast fault injection method suitable for very large scale integration (VLSI). This method can automatically analyze the circuit through scripts, and modify the logic to make the circuit available for fault injection. Experiment results show that the fault injection speed can reach nanosecond level,which can alleviate the contradiction between circuit scale and evaluation time. Consequently, it can meet the evaluation requirements of VLSI.

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SHI Yuzhe, CHEN Xin, CHEN Kai, BAI Yuxin, ZHANG Ying. FPGA Based Single Event Upset Simulation Technology[J].,2021,36(4):822-830.

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History
  • Received:October 22,2020
  • Revised:March 11,2021
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  • Online: July 25,2021
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