This paper analyzes the requirement of sampling clock jitter of high sampling rate and high resolution data acquisition system（DAQ）， and gives the relationship between clock phase noise and clock jitter. The HMC1035LP6GE frequency synthesizer chip is used as the main chip of the clock generation circuit with output clock jitter measured as 90 fs （integer mode， 2 500 MHz output frequency， 100 MHz input frequency， phase detector frequency 100 MHz， loop filter bandwidth 127 kHz， integral interval ［10 kHz， 10 MHz］）. The performance of the circuit in various working conditions is compared， and the corresponding design guidelines are given.