In the ultra-high speed digital phase-locked amplifier (PLA) system, the trade-off between sampling rate and sampling accuracy can be solved by using the conventional time-interleaved parallel analog-to-digital converter (ADC) structure. However, this system is very vulnerable to the impact of sampling clock jitter in each channel. Based on the analysis of the relationship between sampling clock jitter and effective sampling digits and dynamic range, a high-speed digital phase-locked amplifier system is realized by using the parallel ADC alternating sampling structure based on clock tree mechanism. Experimental results show that under the same test conditions, the signal-to-noise ratio of this system is increased by about 17.5 dB compared with that of commercial PLA manufactured by foreign mainstream manufacturers.