High Performance Hardware Architecture of Lattice-Based Cryptography and Its FPGA Implementation
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College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 211106, China

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TN7

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    Abstract:

    With the development of quantum computers, conventional public cryptographic schemes such as RSA and elliptic curve cryptography(ECC) are under serious threat. To resist the quantum attacks, lattice-based cryptography has attracted research attention, in which the ring-learning with error (R-LWE) lattice encryption algorithm has great application potential in the field of encryption because of its easy implementation and quantum attack resistance. From the perspective of hardware application, a parallel circuit architecture of polynomial multiplication in R-LWE encryption scheme is proposed and implemented. The number theoretic transforms (NTT) method and two parallel butterfly operation units are used. The results show that the proposed algorithm can improve the performance by up to 42% with slightly increased hardware resource.

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Rui Kangkang, Wang Chenghua, Fan Sailong, Liu Weiqiang. High Performance Hardware Architecture of Lattice-Based Cryptography and Its FPGA Implementation[J].,2019,34(4):689-696.

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History
  • Received:September 05,2017
  • Revised:December 04,2017
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  • Online: September 01,2019
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