Research and FPGA Implementation of Rapid Code Acquisition for BD2 Signal
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    Abstract:

    Considering the long pseudo-code used by BD2 navigation system with the shortcoming of large resource occupation when employing the traditional matched filter acquisition method, a kind of folded-structure matched filter combined with fast Fourier transform (FFT) is proposed to reduce acquisition time and resource consumption. Firstly, the mathematical model of the algorithm is deduced and the c ore module among sinc interpolation unit is analyzed. The folded-structure and the FFT unit are realized on field-programmable gate array (FPGA). The experiment result show that the design realized rapid acquisition and low resource consumption. The method can be effectively applied to the signal acquiring of BeiDou navigation system as well as that of the other systems.

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Chen Yu, Ji Yuanfa, Sun Xiyan. Research and FPGA Implementation of Rapid Code Acquisition for BD2 Signal[J].,2015,30(3):669-676.

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  • Received:
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  • Online: July 31,2015
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