一种高性能R-LWE格加密算法的电路结构及其FPGA实现
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南京航空航天大学电子信息工程学院,南京,211106

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国家自然科学基金 61771239;江苏省自然科学基金 BK20151477国家自然科学基金(61771239)资助项目;江苏省自然科学基金(BK20151477)资助项目。


High Performance Hardware Architecture of Lattice-Based Cryptography and Its FPGA Implementation
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College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 211106, China

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    摘要:

    随着量子计算机的发展,传统的公钥加密方案,如RSA加密和椭圆曲线加密算法(Elliptic curve cryptography,ECC)受到了严重威胁。为了对抗量子攻击,基于格的密码学引起了关注,其中环错误学习(Ring-learning with error,R-LWE)格加密算法具有电路实现简单、抗量子攻击等优点,在硬件加密领域具有极大的应用潜力。本文从硬件应用的角度,提出并实现了一种R-LWE加密方案中多项式乘法的并行电路结构,采用了数论转换(Number theoretic transforms, NTT)方法,并使用了两个并行的蝶形运算单元。结果表明在增加较少硬件资源的情况下,本文设计的算法提升了42%的运算速度。

    Abstract:

    With the development of quantum computers, conventional public cryptographic schemes such as RSA and elliptic curve cryptography(ECC) are under serious threat. To resist the quantum attacks, lattice-based cryptography has attracted research attention, in which the ring-learning with error (R-LWE) lattice encryption algorithm has great application potential in the field of encryption because of its easy implementation and quantum attack resistance. From the perspective of hardware application, a parallel circuit architecture of polynomial multiplication in R-LWE encryption scheme is proposed and implemented. The number theoretic transforms (NTT) method and two parallel butterfly operation units are used. The results show that the proposed algorithm can improve the performance by up to 42% with slightly increased hardware resource.

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芮康康,王成华,范赛龙,刘伟强.一种高性能R-LWE格加密算法的电路结构及其FPGA实现[J].数据采集与处理,2019,34(4):689-696

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  • 收稿日期:2017-09-05
  • 最后修改日期:2017-12-04
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  • 在线发布日期: 2019-09-01