基于FPGA + SD3.0协议存储速率优化设计
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中国测绘科学研究院航测所,北京 100036

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中国测绘科学研究院基本科研业务费(AR1920);国家重点研发计划(2018YFB0504504);国家自然科学基金重点项目(41730107)。


Storage Rate Optimization Design Based on FPGA+SD3.0 Protocol
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School of Aerial Survey, Chinese Academy of Surveying and Mapping, Beijing 100036,China

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    摘要:

    为解决现有存储方案无法满足在特定功能需求下存储速度与设备体积双重要求的问题,本文设计一种基于现场可编程逻辑门阵列(Field programmable gate array, FPGA)控制的SD3.0版本TF卡控制器,旨在占用最小体积的同时实现更高速的数据存储。通过自行设计的小型数据采集卡,将24 bit位宽的数据经过DDR3、FIFO、RAM、两级缓存最终存入TF卡中。分别从硬件、软件两方面介绍了方案的设计,其中硬件部分主要包括电路工艺、采集卡指标与板级信号完整性验证;软件方面主要包括存储流程、RTL级验证与TF卡测试方案。实验结果表明,本文设计的PCB电路可提供SD3.0协议所需的电压转换和数据存储功能,并且板卡功能稳定,集成度较高,部分TF卡测试的速度超过60 MB/s,长时间测试性能稳定,具有良好的通用性,满足设计要求,为小型化存储实验提供了解决方案。

    Abstract:

    The storage solutions in the market cannot meet the requirements for storage speed and device volume with specific functional requirements. So, we design a SD3.0 version TF card controller based on field programmable gate array(FPGA)control, aiming to achieve higher-speed data storage while occupying the smallest volume. Through a self-designed small data acquisition card, the 24-bit-wide data are finally stored into the TF card through DDR3, FIFO, RAM, and two-level buffer. This paper introduces the scheme design from two aspects of hardware and software. The former mainly includes the circuit technology, acquisition card index and board-level signal integrity verification; the latter mainly includes the storage process, RTL-level verification and the TF card test. Experimental results show that the proposed PCB circuit can provide the voltage conversion and data storage functions required by SD3.0 protocol, and the board has stable functions and high integration. The speed of TF cards exceeds 60 MB/s with a long time. It has stable performance and good versatility. The experiment meets the design requirements, and it can also provide a solution for miniaturized storage experiments.

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许璐,刘正军,陈一铭.基于FPGA + SD3.0协议存储速率优化设计[J].数据采集与处理,2022,37(4):926-934

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  • 收稿日期:2021-03-23
  • 最后修改日期:2022-07-13
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  • 在线发布日期: 2022-08-11