基于FPGA硬件的单粒子翻转模拟技术
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南京航空航天大学电子信息工程学院,南京 211106

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国家自然科学基金(61106029,61701228)资助项目;航空科学基金(20180852005)资助项目;模拟集成电路重点实验室基金(61428020304)资助项目。


FPGA Based Single Event Upset Simulation Technology
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College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 211106, China

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    摘要:

    由于航空航天活动越发复杂,深空通信和姿态控制等航空航天电子系统大量采用集成电路芯片以提高各方面性能。随着集成电路工艺节点的进一步缩小,电路受到单粒子效应而发生错误的概率越来越大。评估集成电路对单粒子翻转(Single event upset, SEU)的敏感性对航空航天的发展具有重要意义。电路规模的增加和系统功能集成度的提高给评估速度带来了严峻挑战。本文提出了一种能适用于超大规模集成电路(Very large scale integration, VLSI)的快速故障注入方法。该方法可通过脚本自动分析电路,并修改逻辑使电路具备故障注入功能。实验结果表明,该方法实现的故障注入速度可以达到纳秒级,可大幅缓解电路规模和评估时间之间的矛盾,从而满足VLSI的评估需求。

    Abstract:

    Due to the increasing complexity of aerospace exploration, integrated circuits are applied in many aerospace electronic systems such as deep space communication and attitude control. With the further shrinking of integrated circuit technology, the probability of errors in circuit due to single event effects has become higher. Evaluating the sensitivity of integrated circuits to single event upset (SEU) is of great significance to the development of aerospace. The continuous increase of circuit scale and the improvement of system function integration pose severe challenges to the speed of evaluation. For this reason, this paper proposes a fast fault injection method suitable for very large scale integration (VLSI). This method can automatically analyze the circuit through scripts, and modify the logic to make the circuit available for fault injection. Experiment results show that the fault injection speed can reach nanosecond level,which can alleviate the contradiction between circuit scale and evaluation time. Consequently, it can meet the evaluation requirements of VLSI.

    表 1 原始逻辑和修改后的逻辑资源开销对比Table 1 Comparison of resource cost between the original and modified logics
    表 3 速度性能对比Table 3 Speed performance comparison
    图1 单触发器结构Fig.1 Structure of flip-flop
    图2 任意触发器故障注入流程Fig.2 Fault injection process of arbitrary flip-flop
    图3 时分复用机制Fig.3 Time division multiplexing mechanism
    图4 提取触发器的脚本流程Fig.4 Script flow of flip-flop extraction
    图5 脚本插入故障逻辑前后对比Fig.5 Comparison of the original logic and the modified logic
    图6 故障注入仿真Fig.6 Fault injection simulation
    图7 系统框架Fig.7 System framework
    表 2 故障注入测试结果Table 2 Fault injection test results
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施聿哲,陈鑫,陈凯,白雨鑫,张颖.基于FPGA硬件的单粒子翻转模拟技术[J].数据采集与处理,2021,36(4):822-830

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  • 收稿日期:2020-10-22
  • 最后修改日期:2021-03-11
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  • 在线发布日期: 2021-09-23